? semiconductor components industries, llc, 2006 november, 2006 ? rev. 5 1 publication order number: mc10h646/d mc10h646, mc100h646 pecl/ttl?ttl 1:8 clock distribution chip description the mc10h/100h646 is a single supply, low skew translating 1:8 clock driver. devices in the on semiconductor h646 translator series utilize the 28 ? lead plcc for optimal power pinning, signal flow through and electrical performance. the single supply h646 is similar to the h643, which is a dual supply 1:8 version of the same function. the h646 was designed specifically to drive series terminated transmission lines. special techniques were used to match the high and low output impedances to about 7.0 . this simplifies the choice of the termination resistor for series terminated applications. to match the high and low output impedances, it was necessary to remove the standard i os limiting resistor. as a result, the user should take care in preventing an output short to ground as the part will be permanently damaged. the h646 device meets all of the requirements for driving the 60 mhz and 66 mhz intel pentium ? microprocessor. the device has no pll components, which greatly simplifies its implementation into a digital design. the eight copi es of the clock allows for point ? to ? point clock distribution to simplify board layout and optimize signal integrity. the h646 provides differential pecl inputs for picking up low skew pecl clocks from the backplane and distributing it to ttl loads on a daughter board. when used in conjunction with the mc10/100e111, very low skew, very wide clock trees can be designed. in addition, a ttl level clock input is provided for flexibility. note that only one of the inputs can be used on a single chip. for correct operation, the unused input pins should be left open. the output enable pin forces the outputs into a high impedance state when a logic 0 is applied. the output buffers of the h646 can drive two series terminated, 50 transmission lines each. this capability allows the h646 to drive up to 16 different point ? to ? point clock loads. refer to the applications section for a more detailed discussion in this area. the 10h version is compatible with mecl ? 10h ecl logic levels. the 100h version is compatible with 100k levels. features ? pecl/ttl ? ttl version of popular eclinps ? e111 ? low skew ? guaranteed skew spec ? tri ? state enable ? differential internal design ? v bb output ? single supply ? extra ttl and ecl power/ground pins ? matched high and low output impedance ? meets specifications required to drive intel ? pentium ? microprocessors ? pb ? free packages are available* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagram* xxx = 10 or 100 a = assembly location wl = wafer lot yy = year ww = work week g= pb ? free package plcc ? 28 fn suffix case 776 mcxxxh646g awlyyww 1 http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions sect ion on page 5 of this data sheet. ordering information
mc10h646, mc100h646 http://onsemi.com 2 ivt q3 ognd q2 ovt q1 ognd q0 q4 ogn d q5 ovt q6 ogn d q7 tclk 1 en ivt ignd v cce v cce v bb eclk 56 7891011 25 24 23 22 21 20 19 26 27 28 2 3 4 18 17 16 15 14 13 12 figure 1. pinout: plcc ? 28 (top view) ignd eclk vee vee vee q0 q1 q2 q3 q4 q5 q6 q7 tclk eclk eclk en figure 2. logic diagram table 1. pin description pin function ognd ovt ignd ivt v ee v cce eclk, eclk v bb q0 ? q7 en ttl output ground (0 v) ttl output v cc (+5.0 v) internal ttl gnd (0 v) internal ttl v cc (+5.0 v) ecl v ee (0 v) ecl ground (5.0 v) differential signal input (pecl) v bb reference output signal outputs (ttl) tri ? state enable input (ttl) table 2. truth table tclk eclk eclk en q gnd gnd h l x l h gnd gnd x h l gnd gnd x h h h h l l h h l z l = low voltage level; h = high voltage level; z = tristate
mc10h646, mc100h646 http://onsemi.com 3 0 100 200 300 400 500 600 700 0 20 40 60 80 100 120 p dynamic = c l ? v swing v cc p to ta l = p static + p dynamic figure 3. output structure internal ttl ground ignd01 ognd0 q0a ovt01 ivt01 internal ttl power figure 4. power versus frequency (typical) frequency, mhz power, mw power versus frequency per bit 300pf 200pf 100pf 50pf no load table 3. 10h pecl dc characteristics (ivt = ovt = v cce = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min typ max min typ max min typ max i inh input high current 255 175 175 a i il input low current 0.5 0.5 0.5 a v ih input high voltage ivt = ivo = v cce = 5.0 v (note 1) 3.83 4.16 3.87 4.19 3.94 4.28 v v il input low voltage ivt = ivo = v cce = 5.0 v (note 1) 3.05 3.52 3.05 3.52 3.05 3.555 v v bb output reference voltage ivt = ivo = v cce = 5.0 v (note 1) 3.62 3.73 3.65 3.75 3.69 3.81 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. ecl v ih , v il and v bb are referenced to v cce and will vary 1:1 with the power supply. the levels shown are for ivt = ivo = v cce = 5.0 v table 4. 100h pecl dc characteristics (ivt = ovt = v cce = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min typ max min typ max min typ max i inh input high current 255 175 175 a i il input low current 0.5 0.5 0.5 a v ih input high voltage ivt = ivo = v cce = 5.0 v (note 2) 3.835 4.12 3.835 4.12 3.835 3.835 v v il input low voltage ivt = ivo = v cce = 5.0 v (note 2) 3.19 3.525 3.19 3.525 3.19 3.525 v v bb output reference voltage ivt = ivo = v cce = 5.0 v (note 2) 3.62 3.74 3.62 3.74 3.62 3.74 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. ecl v ih , v il and v bb are referenced to v cce and will vary 1:1 with the power supply. the levels shown are for ivt = ivo = v cce = 5.0 v
mc10h646, mc100h646 http://onsemi.com 4 table 5. dc characteristics (ivt = ovt = v cce = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min max min max min max v oh output high voltage i oh = 24 ma 2.6 ? ? 2.6 ? ? 2.6 ? ? v v ol output low voltage i ol = 48 ma ? 0.5 ? 0.5 ? 0.5 v ios output short circuit current (note 3) ? ? ? ? ? ? ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. the outputs must not be shorted to ground, as this will result in permanent damage to the device. the high drive outputs of t his device do not include a limiting ios resistor. table 6. ttl dc characteristics (v t = v e = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min max min max min max v ih v il input high voltage input low voltage 2.0 0.8 2.0 0.8 2.0 0.8 v i ih input high current v in = 2.7 v v in = 7.0 v 20 100 20 100 20 100 a i il input low current v in = 0.5 v ? 0.6 ? 0.6 ? 0.6 ma v oh output high voltage i oh = ? 3.0 ma i oh = ? 24 ma 2.5 2.0 2.5 2.0 2.5 2.0 v v ol output low voltage i ol = 24 ma 0.5 0.5 0.5 v v ik input clamp voltage i in = ? 18 ma ? 1.2 ? 1.2 ? 1.2 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. table 7. dc characteristics (ivt = ovt = v cce = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min max min typ max min max i ccl power supply current total all ovt, ivt, and v cce pins 185 166 185 185 ma i cch 175 154 175 175 ma i ccz 210 210 210 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
mc10h646, mc100h646 http://onsemi.com 5 table 8. ac characteristics (ivt = ovt = v cce = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min max min max min max t plh propagation delay eclk to q tclk to q 4.8 5.1 5.8 6.4 5.0 5.3 6.0 6.4 5.6 5.7 6.6 7.0 ns t phl propagation delay eclk to q tclk to q 4.4 4.7 5.4 6.0 4.4 4.8 5.4 5.9 4.8 5.2 5.8 6.5 ns t sk(o) output skew q0, q3, q4, q7 q1, q2, q5 q0 ? q7 (notes 4, 9) 350 350 500 350 350 500 350 350 500 ps t sk(pr) process skew eclk to q tclk to q (notes 5, 9) 1.0 1.3 1.0 1.1 1.0 1.3 ns t sk(p) pulse skew t plh ? t phl 1.0 1.0 1.0 ns t r , t f rise/fall time 0.3 1.5 0.3 1.5 0.3 1.5 ns t pw output pulse width 66 mhz @ 2.0 v 66 mhz @ 0.8 v 60 mhz @ 2.0 v 60 mhz @ 0.8 v (notes 6, 9) 5.5 5.5 6.0 6.0 5.5 5.5 6.0 6.0 5.5 5.5 6.0 6.0 ns t stability clock stability (notes 7, 9) 75 75 75 ps f max maximum input frequency (notes 8, 9) 80 80 80 mhz note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. output skew defined for identical output transitions. 5. process skew is valid for v cc = 5.0 v 5%. 6. parameters guaranteed by t sk(p) and t r , t f specification limits. 7. clock stability is the period variation between two successive rising edges. 8. for series terminated lines. see applications section for f max enhancement techniques. 9. all ac specifications tested driving 50 series terminated transmission lines at 80 mhz. ordering information device package shipping ? mc10h646fn plcc ? 28 37 units / rail mc10h646fng plcc ? 28 (pb ? free) 37 units / rail mc10h646fnr2 plcc ? 28 500 / tape & reel MC10H646FNR2G plcc ? 28 (pb ? free) 500 / tape & reel mc100h646fn plcc ? 28 37 units / rail mc100h646fng plcc ? 28 (pb ? free) 37 units / rail mc100h646fnr2 plcc ? 28 500 / tape & reel mc100h646fnr2g plcc ? 28 (pb ? free) 500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc10h646, mc100h646 http://onsemi.com 6 resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc10h646, mc100h646 http://onsemi.com 7 package dimensions plcc ? 28 fn suffix plastic plcc package case 776 ? 02 issue e ? n ? ? m ? ? l ? v w d d y brk 28 1 view s s l?m s 0.010 (0.250) n s t s l?m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l?m m 0.007 (0.180) n s t ? t ? b s l?m s 0.010 (0.250) n s t s l?m m 0.007 (0.180) n s t u s l?m m 0.007 (0.180) n s t z g1 x view d ? d s l?m m 0.007 (0.180) n s t k1 view s h k f s l?m m 0.007 (0.180) n s t notes: 1. datums ?l?, ?m?, and ?n? determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum ?t?, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 ??? 0.51 ??? k 0.025 ??? 0.64 ??? r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y ??? 0.020 ??? 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 ??? 1.02 ???
mc10h646, mc100h646 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc10h646/d eclinps is a trademark of semiconductor components industries, llc (scillc). mecl 10h is a trademark of motorola, inc. pentium is a registered trademark of intel corporation. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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